In a semiconductor storage device according to the prior art, a non-volatile semiconductor storage device having a cell transistor shown in FIG. 38 is known as a non-volatile semiconductor storage device that stores multiple-bit information per cell (Related Art Example 1). The non-volatile semiconductor storage device according to Related Art Example 1 includes: two band-like regions 123a, 123b formed in a surface layer of a semiconductor substrate 121 so as to embrace a band-like semiconductor layer 124a of a first conductivity type, the regions 123a, 123b being of the opposite conductivity type; a first floating gate 127a formed from the one region 123a of the opposite conductivity type to one side face of the semiconductor layer 124a via an insulating film 122a; a second floating gate 127b formed from the other region 123b of the opposite conductivity type to the other side face of the semiconductor layer 124a via an insulating film 122b; and a control gate 130a formed on the top surface of the semiconductor layer 124a via an insulating film 128 (see the specification of Japanese Patent Number 3249811). In accordance with the non-volatile semiconductor storage device according to Related Art Example 1, the reliability of the structure per se is high, localization of captured electric charge is maintained even if excessive writing is performed, a fluctuation in threshold-value voltage can be suppressed, and it is possible to reduce the size by the amount of overlap between the first floating gates 127a, 127b and regions 123a, 123b of opposite conductivity type.
Further, a non-volatile semiconductor storage device of the kind shown in FIGS. 39 and 40 (Related Art Example 2) is known among the conventional semiconductor storage devices. The non-volatile semiconductor storage device according to Related Art Example 2 comprises the following in a memory cell: a first diffusion region 207a and a second diffusion region 207b provided in spaced-apart relation on the surface of a substrate 201; a select gate 203 provided on the substrate 201 between the first diffusion region 207a and the second diffusion region 207b via an insulating film 202; and a third diffusion region 221 (FIG. 39) provided on the surface of the substrate 201 below the select gate 203 outside the cell area and extending in a direction that intersects the select gate 203; wherein floating gates 206 are provided via the insulating film 202 in a first area between the first diffusion region 207a and the select gate 203 and a second area between the second diffusion region 207b and the select gate 203, and control gates 211 are provided on the floating gates 206 and the select gate 203 via an insulating film 208; the first diffusion region 207a, floating gate 206, control gate 211 and select gate 203 construct a first unit cell, and the second diffusion region 207b, floating gate 206, control gate 211 and select gate 203 construct a second unit cell. An inversion layer 220 is formed on the surface of the substrate 201 below the select gate 203 inside the cell area by applying a positive voltage to the select gate 203. The third diffusion region 221 (FIG. 39) is provided for every erase block (a block comprising a plurality of unit cells in which electrons are pulled in from the floating gates 206 at the same time that an erase operation is performed) and is used as a common source. The first diffusion region 207a and the second diffusion region 207b are used as local bit lines and are electrically connected to a sense amplifier (not shown) via a global bit line (not shown) and switch (not shown). The non-volatile semiconductor storage device according to Related Art Example 2 differs from that of Related Art Example 1 in that (1) the select gate 203 exists; (2) the inversion layer 220 is formed below the select gate 203 inside the cell area when a positive voltage is applied to the select gate 203; (3) the area under the floating gate 206 is used as a channel; and (4) the inversion layer 220 and third diffusion region 221 (FIG. 39) are used in a current-supply path on the drain side at read-out.
Operation of the non-volatile semiconductor storage device according to Related Art Example 2 will be described with reference to the drawings. FIG. 41 is a schematic view useful in describing the read-out operation of the semiconductor storage device according to Related Art Example 2 (the read-out operation when a state in which electrons have not accumulated in a floating gate prevails). FIG. 42 is a schematic view useful in describing the write operation of the semiconductor storage device according to Related Art Example 2. FIG. 43 is a schematic view useful in describing the erase operation of the semiconductor storage device according to Related Art Example 2.
With regard to the read-out operation, as illustrated in FIG. 41, a positive voltage is applied to the control gate 211, select gate 203 and third diffusion region 221 (FIG. 39) in a state in which electrons have not accumulated in the floating gate 206 (the erase state: threshold-value voltage low, ON cell), whereby electrons e travel from the second diffusion region 207b through the channel underlying the floating gate 206, travel through the inversion layer 220 formed below the select gate 203 and migrate to the third diffusion region 221 (FIG. 39). In a state in which electrons have accumulated in the floating gate 206 (the write state: threshold-value voltage high, OFF cell), on the other hand, there is no channel below the floating gate 206 and, hence, no flow of electrons e even if a positive voltage is applied to the control gate 211, select gate 203 and third diffusion region 221 (FIG. 39). Read-out is performed by discriminating data (0/1) based upon whether or not the electrons e flow.
With regard to the write operation, as illustrated in FIG. 42, a positive high voltage (e.g., about 5V) is applied to the control gate 211 (e.g., about 9V) and second diffusion region 207b (e.g., about 5V) and a positive low voltage (e.g., about 2V) of such degree that a current of 1 μA will flow is applied in the memory cell of select gate 203, whereby electrons e travel from the third diffusion region 221 (FIG. 39) through the inversion layer 220, which has been formed below the select gate 203, and flow into the second diffusion region 207b. The substrate 201 is at a ground level. At this time some of the electrons e have a high energy owing to the electric field at the boundary of the select gate 203 and floating gate 206, and therefore the electrons are injected into the floating gate 206 through an insulating film 205 (tunnel oxide film) underlying the floating gate 206.
With regard to the erase operation, as illustrated in FIG. 43, a negative high voltage (e.g., about 9V) is applied to the control gate 211 and a positive high voltage (e.g., about 9V) to the substrate 201, whereby electrons e are pulled in from the floating gate 206 into the substrate 201 through the insulating film 205 (tunnel oxide film) underlying the floating gate 206.
In accordance with the non-volatile semiconductor storage device according to Related Art Example 2, in contradistinction to the non-volatile semiconductor storage device according to Related Art Example 1, read-out is performed using the channel underlying the select gate 203 as a drain. As a result, without the intermediary of a non-target storage node of one unit cell, read-out is performed from a target storage node of another independent unit cell that opposes the non-target storage mode with the select gate 203 interposed therebetween. Since the device essentially functions as a 1-bit cell, an advantage is that stable circuit operation is obtained.
[Patent Document 1]
Japanese Patent No. 3249811